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Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems (edition 2006)
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems by Jean-Pierre Deschamps
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Amazon.com Product Description (ISBN 0471687839, Hardcover)A new approach to the study of arithmetic circuits
In Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, the authors take a novel approach of presenting methods and examples for the synthesis of arithmetic circuits that better reflects the needs of today's computer system designers and engineers. Unlike other publications that limit discussion to arithmetic units for general-purpose computers, this text features a practical focus on embedded systems.
Following an introductory chapter, the publication is divided into two parts. The first part, Mathematical Aspects and Algorithms, includes mathematical background, number representation, addition and subtraction, multiplication, division, other arithmetic operations, and operations in finite fields. The second part, Synthesis of Arithmetic Circuits, includes hardware platforms, general principles of synthesis, adders and subtractors, multipliers, dividers, and other arithmetic primitives. In addition, the publication distinguishes itself with:
* A separate treatment of algorithms and circuits-a more useful presentation for both software and hardware implementations
* Complete executable and synthesizable VHDL models available on the book's companion Web site, allowing readers to generate synthesizable descriptions
* Proposed FPGA implementation examples, namely synthesizable low-level VHDL models for the Spartan II and Virtex families
* Two chapters dedicated to finite field operations
This publication is a must-have resource for students in computer science and embedded system designers, engineers, and researchers in the field of hardware and software computer system design and development.
An Instructor Support FTP site is available from the Wiley editorial department.
(retrieved from Amazon Mon, 30 Sep 2013 14:00:43 -0400)
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