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Structured Computer Organization

by Andrew S. Tanenbaum

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456239,651 (3.88)None
This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies and the latest developments in computer organization and architecture. Tanenbaum's renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the author's popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity. A CD-ROM for assembly language programmers is available for teachers. For all computer professionals and engineers who need an overview or introduction to computer architecture.… (more)

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Indeholder "Preface", "1 Introduction", "1.1 Languages, Levels, and Virtual Machines", "1.2 Contemporary Multilevel Machines", "1.3 Historical Evolution of Multilevel Machines", "1.4 Hardware, Software, and Multilevel Machines", "1.5 Processes", "1.6 Outline of this Book", "2 Computer Systems Organization", "2.1 Processors", "2.1.1 Instruction Execution", "2.1.2 Parallel Instruction Execution", "2.1.3 Processor Classification", "2.2 Memory", "2.2.1 Bits", "2.2.2 Memory Addresses", "2.2.3 Metabits", "2.2.4 Secondary Memory", "2.3 Input/output", "2.3.1 I/O devices", "2.3.2 I/O processors", "2.3.3 Character Codes", "2.3.4 Error-Correcting Codes", "2.3.5 Frequency-dependent codes", "2.4 Computer Networks and Distributed Systems", "2.4.1 Long-Haul Networks", "2.4.2 Telecommunication", "2.4.3 Local Networks", "2.4.4 Distributed Systems", "2.5 Summary", "3. The Digital Logic Level", "3.1 Gates and Boolean Algebra", "3.1.1 Gates", "3.1.2 Boolean Algebra", "3.1.3 Implementation of Boolean Functions", "3.1.4 Circuit Equivalence", "3.2 Basic Digital Logic Circuits", "3.2.1 Integrated Circuits", "3.2.2 Conventional Circuits", "3.2.3 Arithmetic Circuits", "3.2.4 Clocks", "3.3 Memory", "3.3.1 Latches", "3.3.2 Flip-Flops and Registers", "3.3.3 Memory Organization", "3.3.4 Memory Properties", "3.4 Microprocessors and Microcomputers", "3.4.1 Microprocessor Chips", "3.4.2 Microcomputer Buses", "3.4.3 The Z80 Microprocessor", "3.4.4 The 68000 Microprocessor", "3.5 Interfacing", "3.5.1 I/O Chips", "3.5.2 Address Decoding", "3.5.3 An Example Microcomputer", "4 The Microprogramming Level", "4.1 Review of the Digital Logic Level", "4.1.1 Registers", "4.1.2 Buses", "4.1.3 Multiplexers and Decoder", "4.1.4 ALUs and Shifters", "4.1.5 Clocks", "4.1.6 Main Memory", "4.1.7 Component Packaging", "4.2 An Example Microarchitecture", "4.2.1 The Data Path", "4.2.2 Microinstructions", "4.2.3 Microinstruction Timing", "4.2.4 Microinstruction Sequencing", "4.3 An Example Macroarchitecture", "4.3.1 Stacks", "4.3.2 The Macroinstruction Set", "4.4 An Example Microprogram", "4.4.1 The Micro Assembly Language", "4.4.2 The Example Microprogram", "4.4.3 Remarks about the Microprogram", "4.4.4 Perspective", "4.5 Design of the Microprogramming Level", "4.5.1 Horizontal versus Vertical Microprogramming", "4.5.2 Nanoprogramming", "4.5.3 Improving Performance", "4.6 The IBM 370/125 microprogramming level", "4.6.1 The IBM 370/125 Microarchitecture", "4.6.2 IBM 3125 Microinstructions", "4.7 The PDP-11/60 Microprogramming level", "4.7.1 The PDP-11/60 Microarchitecture", "4.7.2 The PDP-11/60 Microinstructions", "4.8 Summary", "5 The Conventional Machine Level", "5.1 Examples of the Conventional Machine Level", "5.1.1 IBM System/370", "5.1.2 DEC PDP-11", "5.1.3 Motorola MC68000", "5.1.4 Zilog Z80", "5.2 Instruction Formats", "5.2.1 Design Criteria for Instruction Formats", "5.2.2 Expanding Opcodes", "5.2.3 Examples of Instruction Formats", "5.3 Addressing", "5.3.1 Immediate Addressing", "5.3.2 Direct Addressing", "5.3.3 Register Addressing", "5.3.4 Indirect Addressing", "5.3.5 Indexing", "5.3.6 Base-Register Addressing", "5.3.7 Stack Addressing", "5.3.8 Addressing on the PDP-11 and the 68000", "5.3.9 Discussion of Addressing Modes", "5.4 Instruction Types", "5.4.1 Data Movement Instructions", "5.4.2 Dyadic Operations", "5.4.3 Monadic Operations", "5.4.4 Comparisons and Conditional Jumps", "5.4.5 Procedure Call Instructions", "5.4.6 Loop Control", "5.4.7 Input/Output", "5.5 Flow of Control", "5.5.1 Sequential Flow of Control and Jumps", "5.5.2 Procedures", "5.5.3 Coroutines", "5.5.4 Traps", "5.5.5 Interrupts", "5.6 Summary", "6 The Operating System Machine Level", "6.1 Implementation of the Operating System Machine Level", "6.2 Virtual I/O Instructions", "6.2.1 Sequential Files", "6.2.2 Random Access Files", "6.2.3 Implementation of Virtual I/O Instructions", "6.2.4 Directory Management Instructions", "6.2.5 IBM 370 Virtual I/O", "6.2.6 UNIX Virtual I/O", "6.2.7 CP/M Virtual I/O", "6.3 Virtual Instructions Used in Parallel Processing", "6.3.1 Process Creation", "6.3.2 Race Conditions", "6.3.3 Process Synchronization Using Semaphores", "6.4 Virtual Memory", "6.4.1 Paging", "6.4.2 Implementation of Paging", "6.4.3 Demand Paging and the Working Set Model", "6.4.4 Page Replacement Policy", "6.4.5 Page Size and Fragmentation", "6.4.6 Cache Memory", "6.4.7 Segmentation", "6.4.8 The MULTICS Virtual Memory", "6.4.9 Virtual Memory on the IBM/370", "6.4.10 Virtual Memory on the PDP-11", "6.4.11 Virtual Memory on the 68000", "6.5 Job Control Languages", "6.6 Summary", "7 The Assembly Language Level", "7.1 Introduction to Assembly Language", "7.1.1 What Is an Assembly Language?", "7.1.2 Format of an Assembly Language Statement", "7.1.3 Comparion of Assembly Languageand Problem-Oriented Languages", "7.1.4 Program Tuning", "7.2 The Assembly Process", "7.2.1 Two-Pass Assemblers", "7.2.2 Pass One", "7.2.3 Pass Two", "7.2.4 Symbol Table", "7.3 Macros", "7.3.1 Macro Definition, Call and Expansion", "7.3.2 Macros with Parameters", "7.3.3 Implementation of a Macro Facility in an Assembler", "7.4 Linking and Loading", "7.4.1 Tasks performed by the Linker", "7.4.2 Structure of an Object Module", "7.4.3 Binding Time and Dynamic Relocation", "7.4.4 Dynamic Linking", "7.5 Summary", "8 Multilevel Machines", "8.1 Methods of Implementing New Levels", "8.1.1 Interpretation", "8.1.2 Translation", "8.1.3 Procedural Extension", "8.2 Design Strategies for Multilevel Machines", "8.2.1 Top-down design", "8.2.2 Bottom-up design", "8.2.3 Middle-out design", "8.3 Program Portability", "8.3.1 A Universal Programming Language", "8.3.2 The Brute Force Approach", "8.3.3 UNCOL", "8.3.4 Abstract Machine Language", "8.3.5 Portable Compilers", "8.3.6 Emulation", "8.4 Self-Virtualizing Machines", "8.4.1 IBM VM/370 system", "8.4.2 Goals of self-virtualizing machines", "8.4.3 Implementation of a self-virtualizing machine", "8.5 The Compiler-Interpreter Interface", "8.5.1 High-Level Interfaces", "8.5.2 Discussion of High-Level Interfaces", "8.6 Summary", "9. Reading List and Bibliography", "9.1 Suggestions for Further Reading", "9.1.1 Introduction and General Works", "9.1.2 Computer Systems Organization", "9.1.3 The Digital Logic Level", "9.1.4 The Microprogramming Level", "9.1.5 The Conventional Machine Level", "9.1.6 The Operating System Machine Level", "9.1.7 The Assembly Language Level", "9.1.8 Multilevel computers", "9.1.9 Binary Numbers and Arithmetic", "9.2 Alphabetical Bibliography", "Appendix A Binary Numbers", "A.1 Finite Precision Numbers", "A.2 Radix Number Systems", "A.3 Conversion from One Radix to Another", "A.4 Negative Binary Numbers", "A.5 Binary Arithmetic", "Appendix B Floating-point Number", "Index".

Glimrende gennemgang af hvordan man designer computere fra transistorer og op til højniveausprog og virtuelle maskiner. ( )
  bnielsen | Jan 19, 2013 |
Indeholder "Preface", "Instructor's preface", "1 Introduction", "1.1 Languages, Levels, and Virtual Machines", "1.2 Contemporary Multilevel Machines", "1.3 Historical Evolution of Multilevel Machines", "1.4 Hardware, Software, and Multilevel Machines", "1.5 Processes", "1.6 Outline of this Book", "2 Computer Systems Organization", "2.1 Processors", "2.1.1 Instruction Execution", "2.1.2 Parallel Instruction Execution", "2.2 Memory", "2.2.1 Bits", "2.2.2 Memory Addresses", "2.2.3 Metabits", "2.2.4 Secondary Memory", " Magnetic tapes", " Magnetic disks", " Magnetic drums", " Optical Memories", "2.3 Input/output", "2.3.1 I/O devices", "2.3.2 I/O processors", "2.3.3 Character Codes", "2.3.4 Error-Correcting Codes", "2.3.5 Frequency-dependent codes", "2.4 Transfer of Information", "2.4.1 Data paths", "2.4.2 Telecommunication", " Modulation", " Asynchronous and synchronous transmission", " Simplex, half-duplex, and full-duplex transmission", "3. The Conventional Machine Level", "3.1 Examples of the Conventional Machine Level", "3.1.1 IBM System/360 and System/370", "3.1.2 CDC 6000, Cyber 70 and Cyber 170", "3.1.3 DEC PDP-11", "3.2 Instruction Formats", "3.2.1 Design criteria for instruction formats", "3.2.2 Expanding opcodes", "3.2.3 Examples of instruction formats", "3.3 Addressing", "3.3.1 Immediate addressing", "3.3.2 Direct addressing", "3.3.3 Register addressing", "3.3.4 Indirect addressing", "3.3.5 Indexing", "3.3.6 Base registers", "3.3.7 Stack addressing", " Reverse Polish", " Evaluation of reverse Polish formulas", "3.3.8 Addressing on the PDP-11", "3.3.9 Discussion of addressing modes", "3.4 Instruction Types", "3.4.1 Data movement instructions", "3.4.2 Dyadic operations", "3.4.3 Monadic operations", "3.4.4 Comparisons and conditional jumps", "3.4.5 Procedure call instructions", "3.4.6 Loop control", "3.4.7 Input/output", "3.5 Representation of Data", "3.5.1 Integers", "3.5.2 Floating-point numbers", "3.5.3 Booleans", "3.5.4 Characters", "3.5.5 Strings", "3.5.6 Arrays", " Dope vectors", " Marginal indexing", "3.6 Flow of Control", "3.6.1 Sequential flow of controls and jumps", "3.6.2 Procedures", "3.6.3 Coroutines", "3.6.4 Traps", "3.6.5 Interrupts", "4 The Microprogramming Level", "4.1 Processor components", "4.1.1 Registers", "4.1.2 Buses", "4.1.3 Gates", "4.1.4 Clocks", "4.1.5 Memory ports", "4.1.6 Arithmetic and logical units", "4.1.7 Packaging of processor components", "4.2 Basic Operations", "4.2.1 Register transfer", "4.2.2 Memory read/write", "4.2.3 Bit testing", "4.3 A Hypothetical Target Level", "4.4 A Hypothetical Host Level", "4.4.1 The host level's registers", "4.4.2 The host level's ALU", "4.4.3 The host level's gates and data paths", "4.5 Gate Sequences", "4.5.1 Subcycles", "4.5.2 Gate sequences for the ADD instruction", "4.6 Microprogrammed Gate Control", "4.6.1 Microinstructions", "4.6.2 Execution of microprograms", "4.6.3 A two-level machine", "4.7 A Language for Microprogramming", "4.7.1 Notation for GATE microinstructions", "4.7.2 Notation for TEST microinstructions", "4.8 The Interpreter for the Target Machine", "4.8.1 Interpretation of the multiplication instruction", "4.8.2 Interpretation of the division instruction", "4.8.3 Perspective", "4.9 Design of the Microprogramming Level", "4.9.1 Encoded fields", "4.9.2 Horizontal versus vertical organization", "4.9.3 Memory cycle ratios and overlapped execution", "4.9.4 Nanomemories", "4.9.5 Universal versus specific microprogramming levels", "4.9.6 Review of microprogramming level organization", "4.10 Advantages and Disadvantages of Microprogramming", "4.11 The IBM 370/125's microprogramming level", "4.11.1 Architecture of the IBM 370/125 microprogramming level", "4.11.2 IBM 3125 microinstructions", "4.12 The PDP-11/40 microprogramming level", "4.12.1 Architecture of the PDP-11/40 microprogramming level", "4.12.2 UNIBUS operation", "4.12.3 PDP-11/40 microinstructions", "4.13 The Burroughs B1700", "4.13.1 Architecture of the B1700", "4.13.2 The B1700 instruction set", "5 The Operating System Machine Level", "5.1 Implementation of the Operating System Machine Level", "5.2 Virtual I/O Instructions", "5.2.1 Sequential files", "5.2.2 Random access files", "5.2.3 Implementation of virtual i/o instructions", "5.2.4 IBM 370 virtual i/o", "5.3 Virtual Instructions Used in Parallel Processing", "5.3.1 Process creation and destruction", "5.3.2 Race conditions", "5.3.3 Process synchronization using semaphores", "5.3.4 Instructions for interprocess communication", "5.4 Other Level 3 Instructions", "5.4.1 Directory management instructions", "5.4.2 Reconfiguring the level 3 machine", "5.5 Virtual Memory", "5.5.1 Paging", "5.5.2 Implementation of paging", "5.5.3 Demand paging and the working set model", "5.5.4 Page replacement policy", "5.5.5 The dirty bit", "5.5.6 The hardware map", "5.5.7 Page size and fragmentation", "5.5.8 Cache memory", "5.5.9 Segmentation", "5.5.10 Virtual memory on the PDP-11", " Checkerboarding", "5.5.11 The MULTICS virtual memory", "5.5.12 Virtual memory on the IBM 370", "5.5.13 Segmented virtual memory and file i/o", "5.6 Job Control Languages", "6 The Assembly Language Level", "6.1 Introduction to Assembly Language", "6.1.1 What is an assembly language", "6.1.2 Format of an assembly language statement", "6.1.3 Comparison of assembly language and PL/I", "6.1.4 Program tuning", "6.2 The Assembly Process", "6.2.1 Two-pass assemblers", "6.2.2 Pass one", "6.2.3 Pass two", "6.3 Searching and Sorting", "6.3.1 Searching", "6.3.2 Linear searching", "6.3.3 Binary searching", "6.3.4 Sorting", "6.3.5 Hash coding", "6.3.6 Hasing functions and collisions", "6.3.7 Comparison of association techniques", "6.4 Macros", "6.4.1 Macro definition, call, and expansion", "6.4.2 Macros with parameters", "6.4.3 Condition macro expansion", "6.4.4 Nested macro calls", "6.4.5 Recursive macro calls", "6.4.6 Nested macro definitions", "6.4.7 Implementation of a macro facility in an assembler", "6.5 Linking and Loading", "6.5.1 Tasks performed by the linker", "6.5.2 Structure of an object module", "6.5.3 Binding time and dynamic relocation", "6.5.4 Dynamic linking", "7 Multilevel Machines", "7.1 Methods of Implementing New Levels", "7.1.1 Interpretation", "7.1.2 Translation", " General-purpose macro processors", "7.1.3 Procedural extension", "7.2 Design Strategies for Multilevel Machines", "7.2.1 Top-down design", "7.2.2 Bottom-up design", "7.2.3 Middle-out design", "7.3 Program Portability", "7.3.1 A univerversal programming language", "7.3.2 The brute force approach", "7.3.3 UNCOL", "7.3.4 Do-it-yourself virtual machines", "7.3.5 Emulation", "7.3.6 Networks", "7.4 Self-Virtualizing Machines", "7.4.1 IBM VM/370 system", "7.4.2 Goals of self-virtualizing machines", " Self-virtualizing machines and time sharing", " Operating system testing", " Protection of confidental data", "7.4.3 Implementation of a self-virtualizing machine", " Exceptions and virtual machine faults", " Simulation of virtual machine i/o", " Selv-modifying channel programs", " Shadow page tables", "7.5 High-Level Machine Architecture", "7.5.1 Addressing and descriptors", "7.5.2 High-level machine instructions", "7.5.3 Advantages and disadvantages of high-level machines", "8 Suggestions for Further Reading and Bibliography", "8.1 Suggestions for Further Reading", "8.1.1 Addressing and instructions", "8.1.2 Assemblers and assembly language programming", "8.1.3 Binary numbers and arithmetic", "8.1.4 Character codes, redundant and nonredundant", "8.1.5 Computer organization", "8.1.6 The conventional machine level", "8.1.7 Deadlocks", "8.1.8 File systems", "8.1.9 High-level machines", "8.1.10 Input/output", "8.1.11 Linkers and loaders", "8.1.12 Macros", "8.1.13 The microprogramming level", "8.1.14 Multilevel computers", "8.1.15 Networks", "8.1.16 Operating systems", "8.1.17 Parallel programming", "8.1.18 Self-virtualizing machines", "8.1.19 Symbol tables", "8.1.20 Telecommunications", "8.1.21 Virtual memory", "8.2 Alphabetical Bibliography", "Appendix A Finite-precision Arithmetic and binary numbers", "A.1 Finite-precision Numbers", "A.2 Radix Number Systems", "A.3 Conversion from One Radix to Another", "A.4 Negative Binary Numbers", "A.5 Binary Arithmetic", "Appendix B Floating-point Number", "Appendix C Boolean Algebra", "Index".

Standardlærebogen på Datalogi-2 i 1980. Alle eksempler er forældede nu til dags. Her i 2020 er det ARM og AMD64, der regerer verden. Flere cores med flere tråde i hver. Og stadigvæk er det svært at udnytte det på en smart måde. Heartbleed og lignende bugs ligger og lurer helt nede på cpu-niveau og gør det umuligt at lave helt sikre systemer. ( )
  bnielsen | Jan 17, 2013 |
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This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies and the latest developments in computer organization and architecture. Tanenbaum's renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the author's popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity. A CD-ROM for assembly language programmers is available for teachers. For all computer professionals and engineers who need an overview or introduction to computer architecture.

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