Click on a thumbnail to go to Google Books.
Loading... Writing Testbenches: Functional Verification of HDL Models, Second Editionby Janick Bergeron
None Loading...
Sign up for LibraryThing to find out whether you'll like this book. No current Talk conversations about this book. No reviews no reviews | add a review
mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification. No library descriptions found. |
Current DiscussionsNone
Google Books — Loading... GenresMelvil Decimal System (DDC)621.3815Technology Engineering and allied operations Applied physics Electrical, magnetic, optical, communications, computer engineering; electronics, lighting Electronics, communications engineering ElectronicsLC ClassificationRatingAverage: No ratings.Is this you?Become a LibraryThing Author. |